The present invention relates to SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit using said SET/RESET latch circuit and Schmitt trigger circuit, in which said SET/RESET latch circuit uses CML(Current Mode Logic)-type 3-port transistors and negative differential resistance diodes.
The DC I-V characteristics of negative differential resistance diode used in the present invention is shown in FIG. 3. A representative example for implementing D-type flip flop circuit by using the diode with negative differential resistance characteristics is MOnostable-BIstable transition Logic Element(MOBILE), where in MOBILE, two negative differential resistance diodes(Resonant Tunneling Diode) are connected in serial as shown in FIG. 1, and a transistor is connected to a negative differential resistance diode in parallel as shown in a US patent(U.S. Pat. No. 5,313,117, Semiconductor logic circuit using two N-type negative resistance devices) and a paper(Monolithic integration of resonant tunneling diode and FET's for Monostable-BIstable transition Logic Elements, IEEE Electron Device Letters, vol. 16, no. 2 Feb. 1995).
However, in the above circuits, the output signal is provided as a Return-to-Zero(RZ)-mode signal. In fact, since Non-Return-to-Zero(NRZ)-mode signal system is utilized for increasing operation speed of system in very high speed optical communication system, it has difficulties in applying RZ-mode MOBILE circuit to very high speed digital circuits. In order to overcome the above disadvantages, a D-type flip flop circuit with NRZ-mode output signal using two MOBILE circuits with RZ-mode output and SET/RESET latch circuit have been reported in a Japan patent(1997-162705, a flip-flip circuit) and a paper(A novel Delayed Flip-Flop circuit using resonant tunneling logic gates, Jpn. J. Appl. Phys., vol. 37, no. 2B, February 1998). Therein, NRZ-mode D-type flip flop circuit is implemented by connecting SET/RESET latch circuit to the MOBILE circuit output stage with RZ-mode output signal.